IN74ACT533DW 데이터 시트보기 (PDF) - Integral Corp.
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IN74ACT533DW Datasheet PDF : 5 Pages
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IN74ACT533
OCTAL 3-STATE INVERTING
TRANSPARENT LATCH
High-Speed Silicon-Gate CMOS
The IN74ACT533 is identical in pinout to the LS/ALS533,
HC/HCT533. The IN74ACT533 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs
change asynchronously) when Latch Enable is high. The data
appears as the outputs in inverted form. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the
latches, but when Output Enable is high, all device outputs are
forced to the high-impedance state. Thus, data may be latched
even when the outputs are not enabled.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
• 3-State Outputs for Bus Interfacing
ORDERING INFORMATION
IN74ACT533N Plastic
IN74ACT533DW SOIC
TA = -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Output Latch D Q
Enable Enable
L
HH L
L
HLH
L
L X no
chang
e
H
XXZ
X = don’t care
Z = high impedance
1
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