SN74LS160AN 데이터 시트보기 (PDF) - ON Semiconductor
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SN74LS160AN Datasheet PDF : 7 Pages
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SN74LS160A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
The positive TC pulse occurs when the outputs are in the
(Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163.
CET
1.3 V
tPLH
1.3 V
tPHL
TC
1.3 V
1.3 V
Figure 3
OTHER CONDITIONS: CP = PE = CEP = MR = H
CLOCK TO TERMINAL COUNT DELAYS
The positive TC pulse is coincident with the output state
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and
(Q0 • Q1 • Q2 • Q3) for the LS161 and LS163.
CP
TC
Figure 4
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: PE = CEP = CET = MR = H
SETUP TIME (ts) AND HOLD TIME (th)
FOR PARALLEL DATA INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(H)
P0 w P1 w P2 w P3
Q0 w Q1 w Q2 w Q3
Figure 5
1.3 V
th(H) = 0 ts(L)
1.3 V
1.3 V
1.3 V
th(L) = 0
1.3 V
OTHER CONDITIONS: PE = L, MR = H
SETUP TIME (ts) AND HOLD TIME (th) FOR
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(L)
SR or PE
1.3 V
1.3 V
th (L) = 0
ts(H)
th(H) = 0
1.3 V
PARALLEL LOAD
(See Fig. 5)
1.3 V
COUNT MODE
(See Fig. 7)
Q RESPONSE TO PE
RESET
COUNT OR LOAD
Q RESPONSE TO SR
Figure 6
CP
ts(H)
CEP
ts(H)
CET 1.3 V
1.3 V
ts(L)
th(H) = 0
1.3 V
th(H) = 0
1.3 V
COUNT
1.3 V
th(L) = 0
1.3 V
ts(L)
1.3 V
HOLD
1.3 V
th(L) = 0
1.3 V
HOLD
Q
OTHER CONDITIONS: PE = H, MR = H
Figure 7
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