UT62L1024LS-55LI(Rev0_1) 데이터 시트보기 (PDF) - Utron Technology Inc

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UT62L1024LS-55LI
(Rev.:Rev0_1)

128K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.1

UT62L1024(I)

128K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = -40℃~+85℃ )

PARAMETER

Vcc for Data Retention

Data Retention Current

SYMBOL TEST CONDITION

VDR

CE 1 ≧ VCC-0.2V or CE2 ≤ 0.2V

IDR

Vcc=2V

-L

CE 1 ≧ VCC-0.2V or

CE2 ≤ 0.2V

- LL

Chip Disable to Data

Retention Time

tCDR See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time

*Those parameters are for reference only under 50℃

MIN.

2.0

-

TYP.

-

5

-

1.5

0

-

MAX.

3.3

50

10*

15

2*

-

UNIT

V

µA

µA

ns

tRC*

-

-

ns

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) ( CE 1 controlled)

Data Retention Mode

VCC

Vcc

VDR ≧ 2V

tCDR

CE1

VIH

CE1 ≧ VCC-0.2V

Vcc

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Data Retention Mode

VCC

Vcc

VDR ≧ 2V

CE2

tCDR

VIL

CE2 ≦ 0.2V

Vcc

tR

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

8

P80078

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