ADP3334 데이터 시트보기 (PDF) - Analog Devices
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ADP3334 Datasheet PDF : 11 Pages
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ADP3334
THEORY OF OPERATION
The new anyCAP LDO ADP3334 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 that is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
OUTPUT
ATTENUATION
Q1
(VBANDG AP / VOUT)
COMPENSATION
R1
CAPACITOR
NONINVERTING
WIDEBAND
DRIVER
PTAT R3 D1
gm
VOS
PTAT
FB (a)
ADP3334
R4 CURRENT
R2
CLOAD
RLOAD
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual band gap” voltage, implicit in
the network although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more
flexibility on the trade-off of noise sources that leads to a low
noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
With the ADP3334 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 mF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
lead to excellent line and load regulation. An impressive ±1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Output Capacitor
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3334 is stable with
a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 1 µF is all that is needed for stability;
larger capacitors can be used if high output current surges are
anticipated. The ADP3334 is stable with extremely low ESR
capacitors (ESR Ϸ 0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types may fall below the minimum over the operating
temperature range or with the application of a dc voltage.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction Capacitor
A noise reduction capacitor (CNR) can be placed between the
output and the feedback pin to further reduce the noise by
6 dB to 10 dB (TPC 18). Low leakage capacitors in the 100 pF
to 1 nF range provide the best performance. Since the feedback
pin (FB) is internally connected to a high impedance node, any
connection to this node should be carefully done to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible, and long PC board traces are not
recommended.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values of 1 nF, this delay may be
on the order of several milliseconds.
VIN
CIN
1F
ADP3334
IN
OUT
IN
OUT
SD
OFF
ON
FB
GND
R1 CNR
R2
VOUT
COUT
1F
Figure 3. Typical Application Circuit
Output Voltage
The ADP3334 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be divided
by R1 and R2 and then fed back to the FB pin.
–6–
REV. C
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