AN-8027 데이터 시트보기 (PDF) - Fairchild Semiconductor
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AN-8027 Datasheet PDF : 17 Pages
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AN-8027
60dB
Control-to-output
40dB
20dB
Compensation
0dB
-20dB
Closed Loop Gain
fIP
fIZ
fIC
-40dB
10Hz 100Hz 1kHz 10kHz 100kHz 1MHz
Figure 17. Current Loop Compensation
Figure 18. Voltage Loop Compensation
(Design Example) Setting the crossover frequency
as 7kHz:
vv))CIESA1
@ f = fIC
=
RCS1 ⋅VBOUT
VRAMP ⋅ 2π fIC ⋅ LBOOST
=
2.55 ⋅ 2π
0.1⋅ 387
⋅ 7 ×103 ⋅ 524 ×10−6
= 0.66
RIC
=
GMI
⋅
1
vv))CIESA1
@ f = fIC
=
1
88 ×10−6
⋅ 0.66
=
17kΩ
CIC1
=
RIC
1
⋅ 2π
fC
/3
=
17 ×103
1
⋅ 2π ⋅ 7 ×103
/3
=
4nF
Setting the pole of the compensator at 70kHz,
CIC 2
=
1
2π ⋅ fIP ⋅ RIC
=
1
2π ⋅ 70 ×103 ⋅17 ×103
= 0.13nF
[STEP-9] PFC Voltage Loop Design
Since FAN480X employs line feed-forward, the power
stage transfer function becomes independent of the line
voltage. Then, the low-frequency, small-signal, control-to-
output transfer function is obtained as:
vˆBOUT ≅ IBOUT ⋅ KMAX ⋅ 1
vˆEA
5
sCBOUT
where:
vˆBOUT ≅ IBOUT ⋅ KMAX ⋅ 1
vˆEA
5
sCBOUT
(37)
(38)
Proportional and integration (PI) control with high-
frequency pole is typically used for compensation. The
compensation zero (fVZ) introduces phase boost, while the
high-frequency compensation pole (fVP) attenuates the
switching ripple, as shown in Figure 18.
The transfer function of the compensation network is
obtained as:
1+ s
vˆCOMP = 2π fVI ⋅ 2π fVZ
vˆOUT
s 1+ s
(39)
2π fVP
where:
fVI
= 2.5
VBOUT
⋅ GMV
2π ⋅ CVC1
,
fVZ
=
2π
1
⋅ RVC
⋅ CVC1
and
fVP
=
2π
1
⋅ RVC
⋅ CVC 2
(40)
The procedure to design the feedback loop is as follows:
(a) Determine the crossover frequency (fVC) around
1/10~1/5 of the line frequency. Since the control-to-
output transfer function of power stage has -20dB/dec
slope and -90o phase at the crossover frequency, as
shown in Figure 18 as 0dB; it is necessary to place the
zero of the compensation network (fVZ) around the
crossover frequency so that 45° phase margin is
obtained. Then, the capacitor CVC1 is determined as:
CVC1
=
GMV ⋅ I BOUT ⋅ K MAX
5 ⋅ CBOUT ⋅ (2π fVC )2
⋅ 2.5
VBOUT
(41)
To place the compensation zero at the crossover
frequency, the compensation resistor is obtained as:
RVC
=
2π
⋅
1
fVC
⋅ CVC1
(42)
(b) Place compensator high-frequency pole (fVP) at least
a decade higher than fC to ensure that it does not
interfere with the phase margin of the voltage
regulation loop at its crossover frequency. It should
also be sufficiently lower than the switching
frequency of the converter so noise can be effectively
attenuated. Then, the capacitor CVC2 is determined as:
CVC 2
=
2π
⋅
1
fVP
⋅ RVC
(43)
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
10
www.fairchildsemi.com
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