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RT5370N Datasheet PDF : 70 Pages
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RT5370
3.1 SCH/DMA registers
Datasheet
Revision August 30, 2010
INT_STATUS (offset: 0x0200,default :0x00000000)
Bits Type Name
Description
31:18
Reserved
17 R/W TX_COHERENT
TX_DMA finds data coherent event when checking ddone bit.
Write 1 to clear the interrupt.
Read to get the raw interrupt status
16 R/W RX_COHERENT
RX_DMA finds data coherent event when checking ddone bit.
Write 1 to clear the interrupt.
Read to get the raw interrupt status
15
R/W MAC_INT_4
MAC interrupt 4: GP timer interrupt
14 R/W MAC_INT_3
MAC interrupt 3: Auto wakeup interrupt
13 R/W MAC_INT_2
MAC interrupt 2: TX status interrupt
12 R/W MAC_INT_1
MAC interrupt 1: Pre-TBTT interrupt
11 R/W MAC_INT_0
MAC interrupt 0: TBTT interrupt
10 RO TX_RX_COHERENT When TX_COHERENT or RX_COHERENT is on, this bit is set
9
R/W MCU_CMD_INT
MCU command interrupt
8
R/W TX_DONE_INT5
TX Queue#5 packet transmit interrupt
Write 1 to clear the interrupt.
7
R/W TX_DONE_INT4
TX Queue#4 packet transmit interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
6
R/W TX_DONE_INT3
TX Queue#3 packet transmit interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
5
R/W TX_DONE_INT2
TX Queue#2 packet transmit interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
4
R/W TX_DONE_INT1
TX Queue#1 packet transmit interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
3
R/W TX_DONE_INT0
TX Queue#0 packet transmit interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
2
R/W RX_DONE_INT
RX packet receive interrupt
Write 1 to clear the interrupt.
Read to get the raw interrupt status
1
R/W TX_DLY_INT
Summary of the whole WPDMA TX related interrupts
Write 1 to clear the interrupt.
Read to get the raw interrupt status
0
R/W RX_DLY_INT
Summary of the whole WPDMA RX related interrupts
Write 1 to clear the interrupt.
Read to get the raw interrupt status
Init Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INT_MASK (offset:0x0204,default :0x00000000)
Bits Type Name
Description
31:18
Reserved
Init Value
17 R/W TX_COHERENT_EN
16 R/W RX_COHERENT_EN
15 R/W MAC_INT4_EN
DSRT5370_ V1. 0_083010
Form No.：QS-073-F02
Rev.：1
Enable for TX_DMA data coherent interrupt
0
Enable for RX_DMA data coherent interrupt
0
MAC interrupt 4: GP timer interrupt
0
Kept by： DCC
-7-
Ret. Time： 5 Years
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