ML4824 데이터 시트보기 (PDF) - Fairchild Semiconductor

부품명

상세내역

일치하는 목록

ML4824

Power Factor Correction and PWM Controller Combo

Fairchild Semiconductor 

ML4824

FUNCTIONAL DESCRIPTION (Continued)

3) The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this

voltage.

The output of the gain modulator is a current signal, in the

form of a full wave rectified sinusoid at twice the line

frequency. This current is applied to the virtual-ground

(negative) input of the current error amplifier. In this way

the gain modulator forms the reference for the current

error loop, and ultimately controls the instantaneous

current draw of the PFC from the power line. The general

form for the output of the gain modulator is:

IGAINMOD

=

IAC × VEAO

VRMS2

×

1V

(1)

More exactly, the output current of the gain modulator is

given by:

IGAINMOD = K × (VEAO − 1.5V) × IAC

where K is in units of V-1.

Note that the output current of the gain modulator is

limited to ≅ 200µA.

Current Error Amplifier

The current error amplifier’s output controls the PFC duty

cycle to keep the average current through the boost

inductor a linear function of the line voltage. At the

inverting input to the current error amplifier, the output

current of the gain modulator is summed with a current

which results from a negative voltage being impressed

upon the ISENSE pin (current into ISENSE ≅ VSENSE/3.5kΩ).

The negative voltage on ISENSE represents the sum of all

currents flowing in the PFC circuit, and is typically derived

from a current sense resistor in series with the negative

terminal of the input bridge rectifier. In higher power

applications, two current transformers are sometimes used,

one to monitor the ID of the boost MOSFET(s) and one to

monitor the IF of the boost diode. As stated above, the

inverting input of the current error amplifier is a virtual

ground. Given this fact, and the arrangement of the duty

cycle modulator polarities internal to the PFC, an increase

in positive current from the gain modulator will cause the

output stage to increase its duty cycle until the voltage on

ISENSE is adequately negative to cancel this increased

current. Similarly, if the gain modulator’s output decreases,

the output duty cycle will decrease, to achieve a less

negative voltage on the ISENSE pin.

Cycle-By-Cycle Current Limiter

The ISENSE pin, as well as being a part of the current

feedback loop, is a direct input to the cycle-by-cycle

current limiter for the PFC section. Should the input

voltage at this pin ever be more negative than -1V, the

output of the PFC will be disabled until the protection flip-

flop is reset by the clock pulse at the start of the next PFC

power cycle.

8

VREF

PFC

OUTPUT

16

VEAO

VFB

15

2.5V

IAC

2

VRMS

4

ISENSE

3

VEA

–

+

GAIN

MODULATOR

1

IEAO

IEA

+

+

–

–

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

Overvoltage Protection

The OVP comparator serves to protect the power circuit

from being subjected to excessive voltages if the load

should suddenly change. A resistor divider from the high

voltage DC output of the PFC is fed to VFB. When the

voltage on VFB exceeds 2.7V, the PFC output driver is shut

down. The PWM section will continue to operate. The

OVP comparator has 125mV of hysteresis, and the PFC

will not restart until the voltage at VFB drops below 2.58V.

The VFB should be set at a level where the active and

passive external power components and the ML4824 are

within their safe operating voltages, but not so low as to

interfere with the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a

negative resistor; an increase in input voltage to the PWM

causes a decrease in the input current. This response

dictates the proper compensation of the two

transconductance error amplifiers. Figure 2 shows the

types of compensation networks most commonly used for

the voltage and current error amplifiers, along with their

respective return points. The current loop compensation is

returned to VREF to produce a soft-start characteristic on

the PFC: as the reference voltage comes up from zero

volts, it creates a differentiated voltage on IEAO which

prevents the PFC from immediately demanding a full duty

cycle on its boost converter.

There are two major concerns when compensating the

voltage loop error amplifier; stability and transient

response. Optimizing interaction between transient

response and stability requires that the error amplifier’s

REV. 1.01 12/7/2000

Share Link: