AV9148F-02 데이터 시트보기 (PDF) - Integrated Circuit Systems
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AV9148F-02 Datasheet PDF : 16 Pages
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ICS9148-02
Pin Descriptions
PIN NUMBER
2, 1
3, 10, 17, 24,
31, 37, 43
4
5
PIN NAME
REF (0:1)
GND
X1
X2
6
7, 15
8
9, 11, 12, 13, 14, 16
18
19
20
21
22
23
25
26
27
28, 34
40
42, 41, 39, 38
36, 35, 33, 32, 30, 29
44
45
46
47
48
MODE
VDD2
PCICLK_F
PCICLK (0:5)
SEL66/60#
SDATA
SCLK
VDD4
48/24MHzA
48/24MHzB
VDD
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
VDD3
VDDL2
CPUCLK (0:3)
SDRAM (0:5)
PWR_DWN#
IOAPIC
VDDL1
CPU3.3-2.5#
VDD1
TYPE
OUT
PWR
IN
OUT
IN
PWR
OUT
OUT
IN
IN
IN
PWR
OUT
OUT
PWR
OUT
IN
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
PWR
IN
PWR
DESCRIPTION
Reference clock Output
Ground (common)
Crystal or reference input, has internal crystal load cap
Crystal output, has internal load cap and feedback
resistor to X1
Input function selection. If Mode is HIGH, then pins 26 & 27
are configured as outputs (SDRAM7 and SDRAM6). If Mode
is LOW, then, pins 26 & 27 are configured as inputs
(PCI_STOP# and CPU_STOP#).
Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
Selects 60MHz or 66.6MHz for SDRAM and CPU
I2C data input
I2C clock input
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHz driver output for USB or Super I/O
Supply for PLL core, nominal 3.3V
SDRAM clock 60/66.6MHz (selected)
Halts PCI Bus (0:5) at logic "0" level when low
SDRAM clock 60/66.6MHz (selected)
Halts CPU clocks at logic "0" level when low
Supply for SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal
CPUCLK clock output, powered by VDDL2
SDRAMs clock at 60 or 66.6MHz (selected)
Powers down chip, active low
IOAPIC clock output, (14.318MHz) powered by VDDL1
Supply for IOAPIC, either 2.5 or 3.3V nominal
3.3 or 2.5 VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor. When connected to VDD, 3.3V Buffer
strength is selected. When connected to GND, 2.5V Buffer
strength is selected.
Supply for REF (0:1), X1, X2, nominal 3.3V
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
2
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