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74ABT573

Octal D-Type Latch with 3-STATE Outputs

Fairchild Semiconductor 

Connection Diagram

Pin Descriptions

Pin Names

D0–D7

LE

OE

O0–O7

Descriptions

Data Inputs

Latch Enable Input (Active HIGH)

3-STATE Output Enable Input

(Active LOW)

3-STATE Latch Outputs

Logic Diagram

Functional Description

The ABT573 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is

HIGH, data on the Dn inputs enters the latches. In this

condition the latches are transparent, i.e., a latch output

will change state each time its D input changes. When

LE is LOW the latches store the information that was

present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are in the bi-state mode. When OE is

HIGH the buffers are in the high impedance mode but

this does not interfere with entering new data into the

latches.

Function Table

Inputs

OE

LE

D

L

H

H

L

H

L

L

L

X

H

X

X

Outputs

O

H

L

O0

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

O0 = Value stored from previous clock cycle

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

©1993 Fairchild Semiconductor Corporation

74ABT573 Rev. 1.4

2

www.fairchildsemi.com

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