UL6264ADG25 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
부품명
상세내역
일치하는 목록
UL6264ADG25 Datasheet PDF : 8 Pages
| |||
UL6264A
Block Diagram
A4
A5
A6
A7
A8
A9
A11
A12
Memory Cell
Array
256 Rows x
256 Columns
A0
A1
A2
A3
A10
Address
Change
Detector
Sense Amplifier/
Write Control Logic
Clock
Generator
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E2
1
VCC
VSS
WG
E1
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not
*
L
*
*
selected
H
*
*
*
High-Z
High-Z
Internal Read
L
H
H
H
High-Z
Read
L
H
H
L
Data Outputs Low-Z
* H or L
Write
L
H
L
*
Data Inputs High-Z
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating
Temperature
Storage Temperature
C-Type
G-Type
K-Type
Symbol
VCC
VI
VO
PD
Ta
Tstg
2
Min.
-0.3
-0.3
-0.3
0
-25
-40
-55
Max.
7
VCC + 0.5
VCC + 0.5
1
70
85
85
125
Unit
V
V
V
W
°C
°C
°C
°C
December 12, 1997
Share Link: 