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MC74HC174AD

Hex D Flip−Flop with Common Clock and Reset

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Hex D Flip-Flop with

Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC54/74HC174A is identical in pinout to the LS174. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of six D flip–flops with common Clock and Reset

inputs. Each flip–flop is loaded with a low–to–high transition of the Clock

input. Reset is asynchronous and active–low.

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 162 FETs or 40.5 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

D0 3

D1 4

D2 6

D3 11

D4 13

D5 14

2 Q0

5 Q1

7 Q2

10 Q3

12 Q4

15 Q5

NONINVERTING

OUTPUTS

CLOCK 9

RESET 1

PIN 16 = VCC

PIN 8 = GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria

Value Units

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Count*

40.5 ea.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Propagation Delay

1.5

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Power Dissipation

5.0

µW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Speed Power Product

.0075 pJ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ *Equivalent to a two–input NAND gate.

MC54/74HC174A

16

1

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

16

1

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

16

1

D SUFFIX

SOIC PACKAGE

CASE 751B–05

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXAD

Ceramic

Plastic

SOIC

PIN ASSIGNMENT

RESET 1

Q0 2

D0 3

D1 4

Q1 5

D2 6

Q2 7

GND 8

16 VCC

15 Q5

14 D5

13 D4

12 Q4

11 D3

10 Q3

9 CLOCK

FUNCTION TABLE

Inputs

Reset Clock

L

X

H

H

H

L

H

Output

D

Q

X

L

H

H

L

L

X No Change

X No Change

10/95

© Motorola, Inc. 1995

1

REV 6

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