CY7C4261V-15JC 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
일치하는 목록
CY7C4261V-15JC Datasheet PDF : 16 Pages
| |||
AC Test Loads and Waveforms (continued) (-10)
VCC/2
50Ω
I/O
Z0 = 50Ω
3.0V
GND
≤ 3 ns
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
All Input Pulses
90%
10%
90%
10%
≤ 3 ns
Switching Characteristics Over the Operating Range
7C4261/71/81/91V- 7C4261/71/81/91V- 7C4261/71/81/91V-
10
15
25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
tS
Clock Cycle Frequency
100
66.7
tA
Data Access Time
2
8
2
10
2
tCLK
Clock Cycle Time
10
15
25
tCLKH
Clock HIGH Time
4.5
6
10
tCLKL
Clock LOW Time
4.5
6
10
tDS
Data Set-up Time
3.5
4
6
tDH
Data Hold Time
0
0
1
tENS
Enable Set-up Time
3.5
4
6
tENH
tRS
Enable Hold Time
Reset Pulse Width[10]
0
0
1
10
15
25
tRSS
Reset Set-up Time
8
10
15
tRSR
Reset Recovery Time
8
10
15
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[11]
10
15
0
0
0
tOE
Output Enable to Output Valid
tOHZ
Output Enable to Output in High Z[11]
3
7
3
10
3
3
7
3
8
3
tWFF
Write Clock to Full Flag
8
10
tREF
Read Clock to Empty Flag
8
10
tPAF
Clock to Programmable Almost-Full Flag
8
10
tPAE
Clock to Programmable Almost-Full Flag
8
10
tSKEW1
Skew Time between Read Clock and Write 5
Clock for Empty Flag and Full Flag
6
10
40 MHz
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
12
ns
12
ns
15
ns
15
ns
15
ns
15
ns
ns
tSKEW2
Skew Time between Read Clock and Write 10
15
18
ns
Clock for Almost-Empty Flag and
Almost-Full Flag
Notes:
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
Document #: 38-06013 Rev. *B
Page 7 of 16
Share Link: 