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SN74LS393
(Rev.:1999)

Dual 4−Stage Binary Counter

ON Semiconductor 

SN74LS393

FUNCTIONAL DESCRIPTION

Each half of the SN74LS393 operates in the Modulo 16

binary sequence, as indicated in the ÷ 16 Truth Table. The

first flip-flop is triggered by HIGH-to-LOW transitions of

the CP input signal. Each of the other flip-flops is triggered

by a HIGH-to-LOW transition of the Q output of the

preceding flip-flop. Thus state changes of the Q outputs do

not occur simultaneously. This means that logic signals

derived from combinations of these outputs will be subject

to decoding spikes and, therefore, should not be used as

clocks for other counters, registers or flip-flops. A HIGH

signal on MR forces all outputs to the LOW state and

prevents counting.

SN74LS393 LOGIC DIAGRAM (one half shown)

CP

K CP J

CD

Q

MR

K CP J

CD

Q

K CP J

CD

Q

K CP J

CD

Q

Q0

Q1

Q2

Q3

TRUTH TABLE

COUNT

0

1

2

3

OUTPUTS

Q3 Q2 Q1 Q0

LLL L

LLLH

L LHL

L LHH

4

LHL L

5

LHLH

6

L HH L

7

L HHH

8

HLL L

9

HLLH

10

HLH L

11

HLHH

12

HHL L

13

HHL H

14

HHH L

15

HHH H

H = HIGH Voltage Level

L = LOW Voltage Level

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