UT6164CLS-12 데이터 시트보기 (PDF) - Utron Technology Inc
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UT6164CLS-12 Datasheet PDF : 10 Pages
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UTRON
Rev. 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
UT6164C
8K X 8 BIT HIGH SPEED CMOS SRAM
DOUT
tAA
tOH
tOH
Data Valid
READ CYCLE 2 ( CE1、CE2 and OE Controlled) (1,3,5,6)
t RC
Address
CE1
t AA
t ACE1
CE2
t ACE2
OE
Dout
t CLZ1
t CLZ2
HIGH-Z
t OLZ
t OE
t CHZ1
t CHZ2
t OHZ
t OH
Data Valid
HIGH-Z
Notes :
1. WE is high for read cycle.
2. Device is continuously selected CE 1 =VIL and CE2=VIH.
3. Address must be valid prior to or coincident with CE 1 and CE2 transition; otherwise tAA is the limiting parameter.
4. OE is low.
5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady
state.
6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than
tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80074
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