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MC54/74HC589
OUTPUT ENABLE 10
SA 14
SHIFT CLOCK 11
SERIAL SHIFT/ 13
PARALLEL LOAD
LATCH CLOCK 12
A 15
B1
PARALLEL
DATA
INPUTS
C2
D3
E4
F5
G6
H7
LOGIC DETAIL
DQ
C
DQ
C
STAGE A
STAGE B
DQ
C
STAGE C*
STAGE D*
STAGE E*
STAGE F*
STAGE G*
STAGE H
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
S
D
CQ
R
DS
CQ
R
DS
CQ
R
VCC
9
QH
MOTOROLA
3–8
High–Speed CMOS Logic Data
DL129 — Rev 6