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MC54HC589J

8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output

Motorola => Freescale 

MC54/74HC589

DEVICE

UNDER

TEST

TEST CIRCUIT

TEST POINT

OUTPUT

1 kΩ

CL*

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

* Includes all probe and jig capacitance

Figure 9.

PIN DESCRIPTIONS

DATA INPUTS

A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Parallel data inputs. Data on these inputs are stored in the

data latch on the rising edge of the Latch Clock input.

SA (Pin 14)

Serial data input. Data on this input is shifted into the shift

register on the rising edge of the Shift Clock input if Serial

Shift/Parallel Load is high. Data on this input is ignored when

Serial Shift/Parallel Load is low.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 13)

Shift register mode control. When a high level is applied to

this pin, the shift register is allowed to serially shift data.

When a low level is applied to this pin, the shift register ac-

cepts parallel data from the data latch.

Shift Clock (Pin 11)

Serial shift clock. A low–to–high transition on this input

shifts data on the serial data input into the shift register and

data in stage H is shifted out QH, being replaced by the data

previously stored in stage G.

Latch Clock (Pin 12)

Data latch clock. A low–to–high transition on this input

loads the parallel data on inputs A–H into the data latch.

Output Enable (Pin 10)

Active–low output enable A high level applied to this pin

forces the QH output into the high impedance state. A low

level enables the output. This control does not affect the

state of the input latch or the shift register.

OUTPUT

QH (Pin 9)

Serial data output. This pin is the output from the last stage

of the shift register. This is a 3–state output.

MOTOROLA

3–6

High–Speed CMOS Logic Data

DL129 — Rev 6

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