IDT71L024
LOW POWER 3V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ADDRESS
OE
CS1
t RC
t AA
t OE
t OLZ (5)
CS2
DATA OUT
t ACS(3)
t CLZ (5)
HIGH IMPEDANCE
t OHZ (5)
t CHZ (5)
DATAOUT VALID
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TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
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NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected; CS1 is LOW and CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
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