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NCP1294ED16

Enhanced Voltage Mode PWM Controller

ON Semiconductor 

NCP1294

of the Soft−Start can be programmed through a capacitance

connected to the SS pin. The constant charging current to the

SS pin is 50 mA (typ).

The VREF (ok) comparator monitors the 3.3 V VREF

output and latches a fault condition if VREF falls below 3.1 V.

The fault condition may also be triggered when the OV pin

voltage rises above 2.0 V or the UV pin voltage falls below

1.0 V. The undervoltage comparator has a built−in hysteresis

of 75 mV (typ). The hysteresis for the OV comparator is

programmable through a resistor connected to the OV pin.

When an OV condition is detected, the overvoltage

hysteresis current of 12.5 mA (typ) is sourced from the pin.

In Figure 6, the fault condition is triggered by pulling the

UV pin to the ground. Immediately, the SS capacitor is

discharged with 5.0 mA of current (typ) and the GATE output

is disabled until the SS voltage reaches the discharge voltage

of 0.3 V (typ). The IC starts the Soft−Start transition again

if the fault condition has recovered as shown in Figure 6.

However, if the fault condition persists, the SS voltage will

stay at 0.1 V until the removal of the fault condition.

Figure 6. The Fault Condition Is Triggered when

the UV Pin Voltage Falls Below 1.0 V. The

Soft−Start Capacitor Is Discharged and the GATE

Output Is Disabled. CH2: Envelop of GATE Output,

CH3: SS Pin with 0.01 mF Capacitor, CH4: UV Pin

Current Sense and Overcurrent Protection

The current can be monitored by the ISENSE pin to achieve

pulse by pulse current limit. Various techniques, such as a

using current sense resistor or current transformer, can be

adopted to derive current signals. The voltage of the ISET pin

sets the threshold for maximum current. As shown in

Figure 7, when the ISENSE pin voltage exceeds the ISET

voltage, the current limit comparator will reset the GATE

latch flip−flop to terminate the GATE pulse.

Figure 7. The GATE Output Is Terminated When

the ISENSE Pin Voltage Reaches the Threshold Set

By the ISET Pin. CH2: ISENSE Pin, CH4: ISET Pin,

CH3: GATE Pin

The current sense signal is prone to leading edge spikes

caused by the switching transition. A RC low−pass filter is

usually applied to the current signals to avoid premature

triggering. However, the low pass filter will inevitably

change the shape of the current pulse and also add cost. The

NCP1294 uses leading edge blanking circuitry that blocks

out the first 150 ns (typ) of each current pulse. This removes

the leading edge spikes without altering the current

waveform. The blanking is disabled during Soft−Start and

when the VCOMP is saturated high so that the minimum

on−time of the controller does not have the additional

blanking period. The max SS detect comparator keeps the

blanking function disabled until SS charges fully. The output

of the max Duty Cycle detector goes high when the error

amplifier output gets saturated high, indicating that the

output voltage has fallen well below its regulation point and

the power supply may be underload stress.

Oscillator and Synchronization

The switching frequency is programmable through a RC

network connected to the RTCT Pin. As shown in Figure 8,

when the RTCT pin reaches 2.0 V, the capacitor is discharged

by a 1.0 mA current source and the Gate signal is disabled.

When the RTCT pin decreases to 1.0 V, the Gate output is

turned on and the discharge current is removed to let the

RTCT pin ramp up. This begins a new switching cycle. The

CT charging time over the switch period sets the maximum

duty cycle clamp which is programmable through the RT

value as shown in the Design Guidelines. At the beginning

of each switching cycle, the SYNC pin generates a 2.5 V,

320 nS (typ) pulse. This pulse can be utilized to synchronize

other power supplies.

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