MSM54V16282 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM54V16282

262,144-Word x 16-Bit Multiport DRAM

Oki Electric Industry 

¡ Semiconductor

MSM54V16282

Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage

to the device.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate.

4. These parameters depend on output loading. Specified values are obtained with the

output open.

5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles

(TRG = "high") and any 8 SC cycles before proper device operation is achieved.

In the case of using an internal refresh counter, a minimum of 8 CAS before RAS

cycles instead of 8 RAS cycles are required.

6. AC measurements assume tT = 5 ns.

7. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.

Also, transition times are measured between VIH and VIL.

8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.

DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.

DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.

10. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) define the time at which the

outputs achieve the open circuit condition, and are not referenced to output voltage

levels. This parameter is sampled and not 100% tested.

11. Either tRCH or tRRH must be satisfied for a read cycle.

12. These parameters are referenced to CAS leading edge of early write cycles, and to

WE leading edge in TRG controlled write cycles and read modify write cycles.

13. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters.

They are included in the data sheet as electrical characteristics only.

If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will

remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD

(Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle, and the data

out will contain data read from the selected cell; If neither of the above sets of

conditions are satisfied, the condition of the data out is indeterminate.

14. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified

tRCD (Max.) limit, then access time is controlled by tCAC.

15. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD

(Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD

(Max.) limit, then access time is controlled by tAA.

16. Input levels at the AC testing are 3.0 V/0 V.

17. Address (A0 - A8) may be changed two times or less while RAS = VIL.

18. Address (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL.

19. This is guaranteed by design. (tSOH/tCOH = tSCA/tCAC - output transition time)

This parameter is not 100% tested.

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