CD40108BMS 데이터 시트보기 (PDF) - Intersil
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CD40108BMS Datasheet PDF : 11 Pages
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Schematic Diagram (Continued)
CD40108BMS
D
VDD
W
VSS
p
n
p
n
A
p
n
QA
B
p
n
QB
ENABLE
VDD
INPUT
OUTPUT
VSS
DETAIL OF
MEMORY CELL
DETAIL OF
3-STATE OUTPUTS
FIGURE 9. (Continued)
trCL
CL
tS(D)
Dn
WE
tfCL
tH(D)
tW(CL)
tH(WE)
tS(WE)
tH(WA)
tS(WA)
tW(WA)
WA
RA
tPLH
Qn
tTLH
tPHL
tTHL
tPHL
FIGURE 10. TIMING DIAGRAM
0.1 µF
VDD 500 µF
ID
CL
1
24
2
23
CL CL
3
22
4
21
5
20
CL
6
19
7
18
CL
8
17
CL
9
16
10
15
PULSE
11
14
GEN. 3
12
13
CL
CL
PULSE
GEN. 2
PULSE
GEN. 1
P.G. 1
P.G. 2
P.G. 3
Qn A, B
tPLH tPHL
tPLH
(FI)
REPETITIVE WAVEFORMS
FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS
7-34
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