M54HCT75 데이터 시트보기 (PDF) - STMicroelectronics

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M54HCT75

4 BIT D TYPE LATCH

STMicroelectronics 

. HIGH SPEED

tPD = 15 ns (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 2 µA (MAX.) AT TA = 25 °C

. COMPATIBLE WITH TTL OUTPUTS

VIH = 2 V (MIN.) VIL = 0.8 V (MAX.)

. OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. PIN AND FUNCTION COMPATIBLE WITH

54/74LS75

DESCRIPTION

TheM54/74HCT75 isahigh speedCMOS4-BITD-TYPE

LATCH fabricated in silicon gate C2MOS technology. It

has the same high speed performance of LSTTL com-

bined withtrueCMOSlow power consumption. Itcontains

two groups of 2-bit latches controlled by an enable input

(G1 • 2 or G3 • 4). These two latch groups can be used

indifferent circuits. Each latch has Q and Q outputs (1Q -

4Q and 1Q - 4Q). The data applied to the data input is

transfered to the Q and Q outputs when the enable input

is taken high and the outputs will follow the data input as

long as the enable input is kept high. When the enable

input is taken low, the information data applied to the data

input isretained atthe outputs. All inputs areequipped with

protection circuits against static discharge and transient

excessvoltage.This integrated circuit has input andoutput

characteristics that are fully compatible with 54/74 LSTTL

logic families. M54/74HCT devices are designed to di-

rectly interface HSC2MOS systems with TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power consumption.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

M54HCT75

M74HCT75

4 BIT D TYPE LATCH

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HCT75F1R

M74HCT75M1R

M74HCT75B1R

M 74H CT 7 5C 1R

PIN CONNECTIONS (top view)

January 1993

NC =

No Internal

Connection

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