ICS9250YF-19 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9250YF-19

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

ICS9250-19

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.

CPU_STOP# is synchronized by the ICS9250-19. All other clocks will continue to run while the CPUCLKs are disabled. The

CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.

CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the

CPUCLKs inside the ICS9250-19.

3. IOAPIC output is stopped Glitch Free by CPUSTOP# going low.

4. PCI_STOP# is shown in a high (true) state.

5. All other clocks continue to run undisturbed.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9250-19. It is used to turn off the PCICLK (0:5) clocks for low power operation.

PCI_STOP# is synchronized by the ICS9250-19 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full

high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK

clock.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the device.

3. All other clocks continue to run undisturbed.

4. CPU_STOP# is shown in a high (true) state.

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