IT851 데이터 시트보기 (PDF) - ITE Tech. INC.

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IT851

Embedded Controller

ITE Tech. INC. 

Contents

7.3.4.11 Wake-Up Enable Register (WUENR3) .................................................................. 170

7.3.4.12 Wake-Up Enable Register (WUENR4) .................................................................. 170

7.3.5 WUC Input Assignments .................................................................................................... 171

7.3.6 Programming Guide ........................................................................................................... 172

7.4 Keyboard Matrix Scan Controller .................................................................................................... 173

7.4.1 Overview............................................................................................................................. 173

7.4.2 Features ............................................................................................................................. 173

7.4.3 EC Interface Registers ....................................................................................................... 173

7.4.3.1 Keyboard Scan Out Low Byte Data Register (KSOLR)......................................... 173

7.4.3.2 Keyboard Scan Out High Byte Data Register (KSOHR) ....................................... 173

7.4.3.3 Keyboard Scan Out Control Register (KSOCTRLR) ............................................. 173

7.4.3.4 Keyboard Scan In Data Register (KSIR) ............................................................... 174

7.4.3.5 Keyboard Scan In Control Register (KSICTRLR).................................................. 174

7.5 General Purpose I/O Port (GPIO) ................................................................................................... 175

7.5.1 Overview............................................................................................................................. 175

7.5.2 Features ............................................................................................................................. 175

7.5.3 EC Interface Registers ....................................................................................................... 175

7.5.3.1 General Control Register (GCR) ........................................................................... 176

7.5.3.2 Port Data Registers A-I (GPDRA-GPDRI)............................................................. 176

7.5.3.3 Port Control n Registers (GPCRn, n = A0-I7)........................................................ 177

7.5.3.4 Output Type Registers A-I (GPOTA-GPOTI)......................................................... 177

7.5.4 Alternate Function Selection .............................................................................................. 179

7.5.5 Programming Guide ........................................................................................................... 181

7.6 EC Clock and Power Management Controller (ECPM) .................................................................. 182

7.6.1 Overview............................................................................................................................. 182

7.6.2 Features ............................................................................................................................. 182

7.6.3 EC Interface Registers ....................................................................................................... 182

7.6.3.1 Clock Frequency Select Register (CFSELR) ........................................................ 182

7.6.3.2 Clock Gating Control 1 Register (CGCTRL1R) ..................................................... 182

7.6.3.3 Clock Gating Control 2 Register (CGCTRL2R) ..................................................... 183

7.6.3.4 PLL Control (PLLCTRL) ........................................................................................ 183

7.7 SM Bus Interface (SMB) ................................................................................................................. 184

7.7.1 Overview............................................................................................................................. 184

7.7.2 Features ............................................................................................................................. 184

7.7.3 Functional Description........................................................................................................ 184

7.7.3.1 SMBUS Master Interface....................................................................................... 184

7.7.3.2 SMBUS Slave Interface ......................................................................................... 185

7.7.3.3 SMBUS Porting Guide ........................................................................................... 186

7.7.4 EC Interface Registers ....................................................................................................... 190

7.7.4.1 Host Status Register (HOSTA).............................................................................. 191

7.7.4.2 Host Control Register (HOCTL)............................................................................. 191

7.7.4.3 Host Command Register (HOCMD) ...................................................................... 192

7.7.4.4 Transmit Slave Address Register (TRASLA) ........................................................ 192

7.7.4.5 Data 0 Register (D0REG)...................................................................................... 192

7.7.4.6 Data 1 Register (D1REG)...................................................................................... 193

7.7.4.7 Host Block Data Byte Register (HOBDB) .............................................................. 193

7.7.4.8 Packet Error Check Register (PECERC)............................................................... 193

7.7.4.9 Receive Slave Address Register (RESLADR) ...................................................... 193

7.7.4.10 Slave Data Register (SLDA).................................................................................. 193

7.7.4.11 SMBUS Pin Control Register (SMBPCTL) ............................................................ 194

7.7.4.12 Slave Status Register (SLSTA) ............................................................................. 194

7.7.4.13 Slave Interrupt Control Register (SICR) ................................................................ 195

7.7.4.14 Notify Device Address Register (NDADR)............................................................. 195

7.7.4.15 Notify Data Low Byte Register (NDLB).................................................................. 195

7.7.4.16 Notify Data High Byte Register (NDHB) ................................................................ 195

7.7.4.17 Host Control Register 2 (HOCTL2)........................................................................ 196

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IT8510E/TE/G V0.7.2

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