MT9042BP 데이터 시트보기 (PDF) - Mitel Networks
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MT9042BP Datasheet PDF : 2 Pages
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MT9042B
®
Multitrunk System Synchronizer
Preliminary Information
Features
ISSUE 1
October 1996
• Meets jitter requirements for AT&T TR62411
Ordering Information
Stratum 3, 4 and Stratum 4 Enhanced for DS1
MT9042BP 28 Pin PLCC
interfaces and for ETSI ETS 300 011 for E1
-40°C to +85°C
•
•
•
•
•
•
interfaces
ed Provides C1.5, C3, C2, C4, C8 and C16 output
nd clock signals
me ign Provides 8kHz ST-BUS framing signals
m es C Selectable 1.544MHz, 2.048MHz or 8kHz input
co D 2 reference signals
e w 04 Accepts reference inputs from two independent
t R Ne T9 sources
o r M Provides bit error free reference switching -
N fo e meets phase slope and MTIE requirements
Se Operates in either Normal, Holdover and
Description
The MT9042B Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
Freerun modes
Applications
• Synchronization and timing control for
multitrunk T1 and E1 systems
• ST-BUS clock and frame pulse sources
• Primary Trunk Rate Converters
The MT9042B is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300
011. It will meet the jitter tolerance, jitter transfer,
intrinsic jitter, frequency accuracy, holdover
accuracy, capture range, phase slope and MTIE
requirements for these specifications.
OSCi
OSCo
PRI
SEC
RSEL
LOS1
LOS2
TRST
VDD VSS
Master
Clock
TIE
Corrector
Circuit
Virtual
Refer-
ence
DPLL
Reference
Select
MUX
Reference
Select
Selected
Refer-
ence
TIE
Corrector
Enable
Automatic/Manual
Control State Machine
State
Select
State
Select
Input
Impairment
Monitor
Guard Time
Circuit
Output
Interface
Circuit
Feedback
Frequency
Select
MUX
MS1 MS2 RST
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
3-97
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