HD74HC563 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD74HC563

Octal Transparent Latches (with 3-state outputs)

Hitachi -> Renesas Electronics 

HD74HC563/HD74HC573

Octal Transparent Latches (with 3-state outputs)

ADE-205-509 (Z)

1st. Edition

Sep. 2000

Description

When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D

inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at

the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is

applied to the output control input, all outputs go to a high impedance state, regardless of what signals are

present at the other inputs and the state of the storage elements.

Features

• High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)

• High Output Current: Fanout of 15 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Function Table

Outputs

Output Control Latch Enable

Data

HD74HC563

HD74HD573

L

H

H

L

H

L

H

L

H

L

L

L

H

X

X

Q0

Q0

X

Z

Z

Q0 : level of Q before the indicated Steady-sate input conditions were established.

Q0 : complement of Q0 or level of Q before the indicated Steady-state input conditions were established.

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