5002B 데이터 시트보기 (PDF) - TDK Corporation
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5002B Datasheet PDF : 23 Pages
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TV Audio Mute: A mute function is provided for all
TV audio outputs. The mute function is controlled by
setting Bit 6 in Register 0. When this bit is set to a
high state(1), all TV audio outputs are attenuated to
at least -60 dB. This will be the default condition at
power-up. When the bit is set to a low state(0), the
audio path will be in normal operating mode. This bit
can be set independent of the volume control such
that the outputs can be muted before any change in
volume, or any switching of audio sources.
AUXILIARY AUDIO OPERATION
The auxiliary port includes stereo audio outputs for a
SCART connector (Aux_Lout, Aux_Rout). The audio
inputs Lin and Rin are the only sources that can be
switched to the auxiliary audio outputs for the 5002B
device. The audio inputs are switched in concert
with the associated video inputs according to Bits 3-
5 in Register 1.
Internal multiplexers allow the Aux_Lout and
Aux_Rout outputs to be configured into either stereo
or mono audio outputs. The two MSBs of Register 3
control the stereo/mono selection according to the
following table:
Bit 7 Bit 6
0
0
0
1
1
0
1
1
Aux_Lout
source
Lin
Lin+Rin
Lin
Rin
Aux_Rout
source
Rin
Lin+Rin
Lin
Rin
At power-up, these bits default to 00 putting the
device in the stereo mode.
The auxiliary audio outputs can be muted by setting
the MSB in Register 0. This bit is set high(1) at
power-up causing the outputs to be muted. Setting
this bit low(0) enables all auxiliary audio outputs.
DIGITAL OUTPUTS
The 5002B provides two programmable digital
outputs, DO_0 and DO_1. These pins are general
purpose outputs programmed by setting Bit 0 and 1
in Register 3. Setting the register bits to 0 puts these
outputs in the logic low state. Setting the register bits
to 1 puts the outputs in the logic high state. Internal
pull-up resistors (approximately 30k) are included
on these pins.
AVPro® 5002B
Dual SCART A/V Switch
SERIAL PORT DEFINITION
Internal functions of the device are monitored and
controlled by a standard inter-IC (I2C)bus. The serial
port operates in a slave mode only and can be
written to or read from. The default address of the
device is 1001000x.
DATA TRANSFERS
A data transfer starts when the SDATA pin is driven
from HIGH to LOW by the bus master while the
SCLK pin is HIGH. On the following eight clock
cycles, the device receives the data on the SDATA
pin and decodes that data to determine if a valid
address has been received. The first seven bits of
information are the address with the eighth bit
indicating whether the cycle is a read (bit is HIGH) or
a write (bit is LOW). If the address is valid for this
device, on the falling SCLK edge of the eighth bit of
data, the device will drive the SDATA pin low and
hold it LOW until the next rising edge of the SCLK
pin to acknowledge the address transfer. The device
will continue to transmit or receive data until the bus
master has issued a stop by driving the SDATA pin
from LOW to HIGH while the SCLK pin is held HIGH
Write Operation: When the read/write bit (bit 8) is
LOW and a valid address is decoded, the device will
receive data from the SDATA pin. The device will
continue to latch data into the registers until a stop
condition is detected. The device generates an
acknowledge after each byte of data written.
Read Operation: When the read/write bit (bit 8) is
HIGH and a valid address is decoded, the device will
transmit the data from the internal register on the
following eight SCLK cycles. Following the transfer
of the register data and the acknowledge from the
master, the device will release the data bus.
Reset: At power-up the serial port defaults to the
states indicated in boldface type. The device also
responds to the system level reset that is transmitted
through the serial port. When the master sends the
address 00000000 followed by the data 00000110,
the device resets to the default condition. The
device also generates an acknowledge.
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