UT621024LC-35LL 데이터 시트보기 (PDF) - Utron Technology Inc
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UT621024LC-35LL Datasheet PDF : 12 Pages
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UTRON
Rev. 1.5
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
tWC
Address
tAW
CE1
tCW1
CE2
tCW2
tAS
tWP
tWR
WE
DOUT
tWHZ
tOW
High-Z
(4)
(4)
tDW
tDH
DIN
Data Valid
WRITE CYCLE 2 ( CE1 and CE2 Controlled) (1,2,5)
Address
tWC
tAW
CE1
tAS
tCW1
tWR
tCW2
CE2
WE
DOUT
DIN
tWHZ
(4)
tWP
High-Z
tDW
tDH
Data Valid
Notes :
1. WE or CE1 must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high
impedance state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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