UT621024PC-55LL 데이터 시트보기 (PDF) - Utron Technology Inc

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UT621024PC-55LL

128K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Rev. 1.5

UT621024

128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

DOUT

tAA

tOH

tOH

Data Valid

READ CYCLE 2 ( CE1 , CE2 and OE Controlled) (1,3,5,6)

Address

CE1

CE2

OE

DOUT

tRC

tAA

tACE1

tCLZ1

tCLZ2

High-Z

tACE2

tOE

tOLZ

tCHZ1

tCHZ2 tOHZ

tOH

Data Valid

High-Z

Notes :

1. WE is HIGH for read cycle.

2. Device is continuously selected CE1 =VIL and CE2=VIH.

3. Address must be valid prior to or coincident with CE1 and CE2 transition; otherwise tAA is the limiting parameter.

4. OE is low.

5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.

6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.

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UTRON TECHNOLOGY INC.

P80036

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

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