SAA7126H 데이터 시트보기 (PDF) - Philips Electronics
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SAA7126H Datasheet PDF : 44 Pages
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Philips Semiconductors
Digital video encoder
Product specification
SAA7126H; SAA7127H
Table 8 Subaddress 29H
DATA BYTE
BE
LOGIC
LEVEL
DESCRIPTION
− ending point of burst in clock cycles
SRES
0 pin 19 is Real-Time Control Input (RTCI)
1 pin 19 is Sync Reset input (SRES)
REMARKS
PAL: BE = 29 (1DH); default after reset
NTSC: BE = 29 (1DH)
a HIGH impulse resets synchronization of the
encoder (first field, first line)
Table 9 Subaddresses 2AH to 2CH
DATA BYTE
CG
CGEN
LOGIC
LEVEL
DESCRIPTION
− LSB of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.
0 copy generation data output is disabled; default after reset
1 copy generation data output is enabled
Table 10 Subaddress 2DH
DATA BYTE
BTRI
GTRI
RTRI
CVBSTRI
CEN
CVBSEN
VBSEN0
VBSEN1
LOGIC
LEVEL
DESCRIPTION
0 DAC for BLUE output in 3-state mode (high-impedance)
1 DAC for BLUE output in normal operation mode; default after reset
0 DAC for GREEN output in 3-state mode (high-impedance)
1 DAC for GREEN output in normal operation mode; default after reset
0 DAC for RED output in 3-state mode (high-impedance)
1 DAC for RED output in normal operation mode; default after reset
0 DAC for CVBS output in 3-state mode (high-impedance)
1 DAC for CVBS output in normal operation mode; default after reset
0 RED output signal is switched to R DAC; default after reset
1 chrominance output signal is switched to R DAC
0 BLUE output signal is switched to B DAC; default after reset
1 CVBS output signal is switched to B DAC
0 if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset
1 if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC
0 GREEN output signal is switched to G DAC; default after reset
1 luminance (VBS) output signal is switched to G DAC
2002 Oct 15
14
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