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PA9542A Datasheet PDF : 15 Pages
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Philips Semiconductors
2-channel I2C multiplexer and interrupt logic
Product data sheet
PCA9542A
AC CHARACTERISTICS
SYMBOL
PARAMETER
tpd
fSCL
tBUF
tHD;STA
Propagation delay from SDA to SDn or SCL to SCn
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
STANDARD-MODE
I2C-bus
MIN
MAX
—
0.31
0
100
4.7
—
4.0
—
FAST-MODE
I2C-bus
MIN
MAX
—
0.31
0
400
1.3
—
0.6
—
UNIT
ns
kHz
µs
µs
tLOW
LOW period of the SCL clock
4.7
—
1.3
—
µs
tHIGH
HIGH period of the SCL clock
4.0
—
0.6
—
µs
tSU;STA Set-up time for a repeated START condition
4.7
—
0.6
—
µs
tSU;STO
tHD;DAT
Set-up time for STOP condition
Data hold time
4.0
—
0.6
—
µs
02
3.45
02
0.9
µs
tSU;DAT
tR
tF
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
250
—
100
—
ns
—
1000
20 + 0.1Cb3
300
ns
—
300
20 + 0.1Cb3
300
µs
Cb
Capacitive load for each bus line
—
400
—
400
µs
tSP
Pulse width of spikes which must be suppressed
by the input filter
—
50
—
50
ns
tVD:DATL4
tVD:DATH4
Data valid (HL)
Data valid (LH)
—
1
—
1
µs
—
0.6
—
0.6
µs
tVD:ACK Data valid Acknowledge
—
1
—
1
µs
INT
tiv
INTn to INT active valid time4
—
4
—
4
µs
tir
INTn to INT inactive delay time4
—
2
—
2
µs
Lpwr
LOW level pulse width rejection of INTn inputs4
10
—
1
—
ns
Hpwr
HIGH level pulse width rejection of INTn inputs4
500
—
500
—
ns
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
4. Measurements taken with a 1 kΩ pull-up resistor and 50 pF load.
SDA
tBUF
tLOW
tR
tF
SCL
P
tHD;STA
S
tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
Figure 13. Definition of timing on the I2C-bus
tSP
tSU;STO
P
SU00645
2004 Sep 29
11
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