M38504M6-FP 데이터 시트보기 (PDF) - Renesas Electronics

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M38504M6-FP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

List of figures

Fig. 2.2.14 Sequence of check of interrupt request bit .......................................................... 2-19

Fig. 2.3.1 Memory map of registers relevant to timers .......................................................... 2-20

Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-20

Fig. 2.3.3 Structure of Timer 1 .................................................................................................. 2-21

Fig. 2.3.4 Structure of Timer 2 .................................................................................................. 2-21

Fig. 2.3.5 Structure of Timer X, Timer Y ................................................................................. 2-22

Fig. 2.3.6 Structure of Timer XY mode register ...................................................................... 2-23

Fig. 2.3.7 Structure of Timer count source selection register ............................................... 2-24

Fig. 2.3.8 Structure of Interrupt request register 1 ................................................................. 2-25

Fig. 2.3.9 Structure of Interrupt request register 2 ................................................................. 2-25

Fig. 2.3.10 Structure of Interrupt control register 1 ................................................................ 2-26

Fig. 2.3.11 Structure of Interrupt control register 2 ................................................................ 2-26

Fig. 2.3.12 Timers connection and setting of division ratios ................................................. 2-28

Fig. 2.3.13 Relevant registers setting ....................................................................................... 2-28

Fig. 2.3.14 Control procedure ..................................................................................................... 2-29

Fig. 2.3.15 Peripheral circuit example ....................................................................................... 2-30

Fig. 2.3.16 Timers connection and setting of division ratios ................................................. 2-30

Fig. 2.3.17 Relevant registers setting ....................................................................................... 2-31

Fig. 2.3.18 Control procedure ..................................................................................................... 2-32

Fig. 2.3.19 Judgment method of valid/invalid of input pulses ............................................... 2-33

Fig. 2.3.20 Relevant registers setting ....................................................................................... 2-34

Fig. 2.3.21 Control procedure ..................................................................................................... 2-35

Fig. 2.3.22 Timers connection and setting of division ratios ................................................. 2-36

Fig. 2.3.23 Relevant registers setting ....................................................................................... 2-37

Fig. 2.3.24 Control procedure ..................................................................................................... 2-38

Fig. 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-40

Fig. 2.4.2 Structure of Serial I/O2 control register 1 .............................................................. 2-41

Fig. 2.4.3 Structure of Serial I/O2 control register 2 .............................................................. 2-41

Fig. 2.4.4 Structure of Serial I/O2 register ............................................................................... 2-42

Fig. 2.4.5 Structure of Transmit/Receive buffer register ........................................................ 2-42

Fig. 2.4.6 Structure of Serial I/O1 status register ................................................................... 2-43

Fig. 2.4.7 Structure of Serial I/O1 control register .................................................................. 2-44

Fig. 2.4.8 Structure of UART control register .......................................................................... 2-44

Fig. 2.4.9 Structure of Baud rate generator ............................................................................. 2-45

Fig. 2.4.10 Structure of Interrupt edge selection register ...................................................... 2-45

Fig. 2.4.11 Structure of Interrupt request register 1 ............................................................... 2-46

Fig. 2.4.12 Structure of Interrupt request register 2 ............................................................... 2-46

Fig. 2.4.13 Structure of Interrupt control register 1 ................................................................ 2-47

Fig. 2.4.14 Structure of Interrupt control register 2 ................................................................ 2-47

Fig. 2.4.15 Serial I/O connection examples (1) ....................................................................... 2-48

Fig. 2.4.16 Serial I/O connection examples (2) ....................................................................... 2-49

Fig. 2.4.17 Serial I/O transfer data format ............................................................................... 2-50

Fig. 2.4.18 Connection diagram ................................................................................................. 2-51

Fig. 2.4.19 Timing chart .............................................................................................................. 2-51

Fig. 2.4.20 Registers setting relevant to transmitting side ..................................................... 2-52

Fig. 2.4.21 Registers setting relevant to receiving side ......................................................... 2-53

Fig. 2.4.22 Control procedure of transmitting side .................................................................. 2-54

Fig. 2.4.23 Control procedure of receiving side ...................................................................... 2-55

Fig. 2.4.24 Connection diagram ................................................................................................. 2-56

Fig. 2.4.25 Timing chart (Serial I/O1) ....................................................................................... 2-56

Fig. 2.4.26 Registers setting relevant to Serial I/O1 .............................................................. 2-57

Fig. 2.4.27 Setting of serial I/O1 transmission data ............................................................... 2-57

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3850 Group (Spec. H) User’s Manual

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