MT8960 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT8960 Datasheet PDF : 32 Pages
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MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Sym. Min. Typ.* Max Units Test Conditions
1
Clock Frequency
C2i
fC 2.046 2.048 2.05 MHz See Note 3
2
Clock Rise Time
C2i
tCR
50
ns
3
Clock Fall Time
C2i
tCF
50
ns
4
Clock Duty Cycle
C2i
40
50
60
%
5
Chip Enable Rise Time F1i
tER
6
Chip Enable Fall Time F1i
tEF
7
Chip Enable Setup Time F1i
tES
50
8 D Chip Enable Hold Time F1i
tEH
25
9 I Output Rise Time
DSTo
tOR
10 G Output Fall Time
I
DSTo
tOF
11 T Propagation Delay Clock DSTo tPZL
A to Output Enable
tPZH
12 L Propagation Delay
Clock to Output
DSTo
tPLH
tPHL
13
Input Rise Time
CSTi
tIR
DSTi
100 ns
100 ns
ns See Note 4
ns See Note 4
100 ns
100 ns
122 ns
122
ns RL=10 KΩ to VCC
100
ns CL=100 pF
100 ns
100 ns
100 ns
14
Input Fall Time
CSTi
tIF
DSTi
100 ns
100 ns
15
Input Setup Time
CSTi
tISH
25
ns
DSTi
tISL
0
ns
16
Input Hold Time
CSTi
tIH
60
ns
DSTi
60
ns
17 D Propagation Delay
I Clock to SD Output
SD
tPCS
18 G SD Output Fall Time
I
SD
tSF
19 T SD Output Rise Time
SD
tSR
20 A Digital Loopback
L Time DSTi to DSTo
tDL
400
ns CL = 100 pF
200
ns CL = 20 pF
400 ns
122 ns
(See Figures 9a, 9b, 9c)
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 3: The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to
C2i. The A/D and D/A functions are unaffected by changes in clock frequency.
Note 4: This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an
undetermined state to the internally synchronized enable signal.
16
Zarlink Semiconductor Inc.
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