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SL74HCT125N

Quad 3-State Noninverting Buffers

System Logic Semiconductor 

SL74HCT125

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)

Symbol

Parameter

tPLH, tPHL

tPLZ, tPHZ

tPZL, tPZH

tTLH, tTHL

CIN

COUT

Maximum Propagation Delay, Input A to

Output Y (Figures 1 and 3)

Maximum Propagation Delay, Output Enable toY

(Figures 2 and 4)

Maximum Propagation Delay, Output Enable toY

(Figures 2 and 4)

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

Maximum Input Capacitance

Maximum Three-State Output Capacitance

(Output in High-Impedance State)

Guaranteed Limit

25 °C to ≤85°C ≤125°C Unit

-55°C

18

23

27

ns

24

30

36

ns

18

23

27

ns

12

15

18

ns

10

10

10

pF

15

15

15

pF

Power Dissipation Capacitance (Per Buffer)

CPD Used to determine the no-load dynamic power

consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

48

pF

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

SLS

System Logic

Semiconductor

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