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TEA1751LT

HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller

NXP Semiconductors. 

NXP Semiconductors

TEA1751LT

HV start-up flyback controller with integrated PFC controller

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Fig 5. Soft-start-up of PFC

DDD

7.2.6 Low-power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. The power factor correction circuit

is then switched off to maintain high efficiency.

During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of

2.7 V and a maximum voltage of 3.9 V. The lower clamp voltage limits the maximum

power that is delivered when the PFC is switched on again. The upper clamp voltage

ensures that the PFC returns to its normal regulation point in a limited time when returning

from low-power mode.

When the flyback converter leaves the frequency reduction mode, the power factor

correction circuit restores normal operation. To prevent continuous switching of the PFC

circuit, a small hysteresis is built in (75 mV on the FBCTRL pin).

7.2.7 Dual-boost PFC

The mains input voltage modulates the PFC output voltage. The mains input voltage is

measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below

2.2 V, the current is sourced from the VOSENSE pin. To ensure the stable switch-over, a

200 mV transition region is inserted around the 2.2 V, see Figure 6.

At low VINSENSE input voltages, the output current is 15 A. This output current, in

combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage

level at low mains voltages. At high mains input voltages, the current is switched to zero.

The PFC output voltage is then at its maximum. As this current is zero in this situation, it

does not affect the accuracy of the PFC output voltage.

To ensure proper switch-off, the VOSENSE current switches to its maximum value of

15 A when the voltage on pin VOSENSE drops below 2.1 V.

TEA1751LT

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3. — 9 January 2013

© NXP B.V. 2013. All rights reserved.

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