LGGQ 데이터 시트보기 (PDF) - Linear Technology

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LGGQ

42V, 4A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current

Linear Technology 

LT8614

Pin Functions

SYNC/MODE (Pin 17): External Clock Synchronization

Input. Ground this pin for low ripple Burst Mode operation

at low output loads. Tie to a clock source for synchroniza-

tion to an external frequency. Apply a DC voltage of 3V or

higher or tie to INTVCC for pulse-skipping mode. When

in pulse-skipping mode, the IQ will increase to several

hundred µA. Do not float this pin.

GND (Pins 18): LT8614 Ground Pin. Connect this pin to

system ground and to the ground plane.

PG (Pin 19): The PG pin is the open-drain output of an

internal comparator. PG remains low until the FB pin is

within ±9% of the final regulation voltage, and there are

no fault conditions. PG is valid when VIN is above 3.4V,

regardless of EN/UV pin state.

FB (Pin 20): The LT8614 regulates the FB pin to 0.970V.

Connect the feedback resistor divider tap to this pin. Also,

connect a phase lead capacitor between FB and VOUT.

Typically, this capacitor is 4.7pF to 22pF.

SW (Exposed Pad Pins 21, 22): The exposed pads should

to connected and soldered to the SW trace for good thermal

performance. If necessary due to manufacturing limita-

tions Pins 21 and 22 may be left disconnected, however

thermal performance will be degraded.

Block Diagram

VIN

4 VIN1

CIN3

CIN1

INTERNAL 0.97V REF

R3

1V +

OPT

EN/UV

14

– SHDN

R4

OPT

PG

19

VOUT

ERROR

±9%

AMP

++–

C1 R1

R2

FB

20

CSS

OPT

TR/SS

16

SHDN

TSD

INTVCC UVLO

VIN UVLO

2.2µA

RT

RT

15

17 SYNC/MODE

–

+

SLOPE COMP

OSCILLATOR

200kHz TO 3MHz

VC

BURST

DETECT

3.4V

REG

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

SHDN

TSD

VIN UVLO

GND

18

VIN2 13

BIAS

1

INTVCC

2

BST

3

M1

SW

8, 9, 21, 22

M2

GND1

6, 7

GND2

10, 11

CIN2

CVCC

CBST

L

COUT

VOUT

8614 BD

10

For more information www.linear.com/LT8614

8614fb

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