WM8804GEDS 데이터 시트보기 (PDF) - Cirrus Logic

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WM8804GEDS

1:1 Digital Interface Transceiver with PLL

Cirrus Logic 

Production Data

WM8804

When the device powers up, all power up configuration pins are configured as inputs for a minimum

of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based

on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled

and the device to be configured before the pins are released to their selected operating conditions.

Figure 7 illustrates how SDIN is sampled.

Sampling of pin value at reset to

generate internal signals.

SDIN

DQ

RSTB

Power- POR_B

On Reset

ENB

Figure 7 Pin Sampling On Power Up or Hardware Reset

HWMODE

/

SWMODE

If the device is powered up in software control mode, all functions of the device are powered down by

default and must be powered up individually by writing to the relevant bits of the PWRDN register

(Table 7). In hardware control mode, all functions of the device are powered up by default.

REGISTER ADDRESS BIT

LABEL

R30

0

PLLPD

PWRDN

1Eh

1 SPDIFRXP

D

2 SPDIFTXPD

3

OSCPD

4

AIFPD

5

TRIOP

Table 7 Power Down Register

DEFAULT

1

1

1

0

0

0

DESCRIPTION

PLL powerdown

0 = PLL enabled

1 = PLL disabled

S/PDIF receiver powerdown

0 = S/PDIF receiver enabled

1 = S/PDIF receiver disabled

S/PDIF transmitter powerdown

0 = S/PDIF transmitter enabled

1 = S/PDIF transmitter disabled

Oscillator power down

0 = Power Up

1 = Power Down

Digital audio interface power

down

0 = Power Up

1= Power Down

Tri-state all outputs

0 = Outputs not tri-stated

1 = Outputs tri-stated

w

PD Rev 4.1 September 2007

13

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