W173GT 데이터 시트보기 (PDF) - Silicon Laboratories
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W173GT Datasheet PDF : 5 Pages
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W173
Pin Definitions [1]
Pin Name
OE
13.2MHZ
6.6MHZ
10MHZ
50MHZ
X1
X2
VDD
GND
Pin No.
5
13
15
10
7
2
3
1, 6, 9, 12, 16
4, 8, 11, 14
Pin Type
I
O
O
O
O
I
O
P
G
Pin Description
Output Enable: When LOW, this input signal puts all outputs into a high-impedance
state.
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 13.2 MHz.
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 6.6 MHz.
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 10.0 MHz.
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 50.0 MHz.
External Crystal Connection: This pin has dual functions. It can be used as an
external 26.5625 MHz crystal connection or as an external reference frequency
input.
External Crystal Connection: An input connection for an external 26.5625 MHz
crystal. If using an external reference, this pin must be left unconnected.
Power Supply Connections: Connect both VDD pins to the same voltage, either
3.3V or 5.0V. Each VDD pin should have a decoupling capacitor (such as 0.1 µF)
placed as close to the pin as possible.
Ground Connections: Connect all ground pins to the common system ground
plane.
Note:
1. All inputs, except X1 or X2, have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.
......... Document #: 38-07313 Rev. *B Page Page 2 of 5 of 5
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