74AHC373D,118 데이터 시트보기 (PDF) - NXP Semiconductors.
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74AHC373D,118 Datasheet PDF : 17 Pages
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NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Table 2.
Symbol
D7
Q7
VCC
Pin description …continued
Pin
Description
18
data input
19
3-state latch output
20
supply voltage
6. Functional description
Table 3. Function table[1]
Operating mode
Control
OE
LE
Enable and read register (transparent mode) L
H
Latch and read register
L
L
Latch register and disable outputs
H
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Input
Dn
L
H
l
h
X
X
Internal
latch
L
H
L
H
X
X
Output
Q0 to Q7
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
VI
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < −0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
Tamb = −40 °C to +125 °C
−0.5
−0.5
[1] −20
[1] −20
−25
-
−75
−65
[2] -
+7.0 V
+7.0 V
-
mA
+20 mA
+25 mA
+75 mA
-
mA
+150 °C
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT373_3
Product data sheet
Rev. 03 — 20 May 2008
© NXP B.V. 2008. All rights reserved.
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