LFE3-150EA-6FN1156CTW 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFE3-150EA-6FN1156CTW

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

Figure 2-1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level)

JTAG

sysIO

Bank 0

sysIO

Bank 1

Configuration Logic:

Dual-boot, Encryption

and Transparent Updates

On-chip Oscillator

Enhanced DSP

Slices: Multiply,

Accumulate and ALU

sysIO

Bank

7

sysCLOCK

PLLs & DLLs:

Frequency Synthesis

and Clock Alignment

sysMEM Block

RAM: 18 Kbit

Programmable

Function Units:

Up to 149K LUTs

sysIO Bank 6

sysIO

Bank

2

Pre-engineered Source

Synchronous Support:

DDR3 - 800 Mbps

Generic - Up to 1 Gbps

Flexible sysIO:

LVCMOS, HSTL,

SSTL, LVDS

Up to 486 I/Os

SERDES/PCS SERDES/PCS

CH 3

CH 2

SERDES/PCS SERDES/PCS

CH 1

CH 0

sysIO Bank 3

Flexible Routing:

Optimized for speed

and routability

3.2 Gbps SERDES

Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices.

PFU Blocks

The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF.

The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF

blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-

der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2-2. Each slice contains

two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs

associated with each PFU block.

2-2

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