SI1141(2011) 데이터 시트보기 (PDF) - Silicon Laboratories
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SI1141 Datasheet PDF : 66 Pages
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Pin Name
LED1
Si1141/42/43
Table 9. Resource Summary for Hardware Pins
LED Current Drive
Output Drive Disable
Analog Voltage Input
Enable
LED1_I in PSLED12[3:0]
ANA_IN_KEY[31:0]
LED2
LED2_I in PSLED12[7:4]
HW_KEY[7:0]
ANA_IN_KEY[31:0]
LED3
LED3_I in PSLED3[3:0]
HW_KEY[7:0]
INT
INT_OE in INT_CFG[0]
ANA_IN_KEY[31:0]
The interrupts of the Si1141/42/43 are controlled through the INT_CFG, IRQ_ENABLE, IRQ_MODE1,
IRQ_MODE2 and IRQ_STATUS registers.
The INT hardware pin is enabled through the INT_OE bit in the INT_CFG register. The hardware essentially
performs an AND function between the IRQ_ENABLE register and IRQ_STATUS register. After this AND function,
if any bits are set, the INT pin is asserted. The INT_MODE bit in the INT_CFG register is conceptually a method of
determining how the INT pin is deasserted. When INT_MODE = 0, the host is responsible for clearing the interrupt
by writing to the INT_STATUS register. When the specific bits of the INT_STATUS register is written with '1', that
specific INT_STATUS bit is cleared.
Typically, the host software is expected to read the INT_STATUS register, stores a local copy, and then writes the
same value back to the INT_STATUS to clear the interrupt source. Unless specifically stated, INT_MODE should
be zero for normal interrupt handling operation. In summary, the INT_CFG register is normally written with '1'.
The IRQ_MODE1, IRQ_MODE2 and IRQ_ENABLE registers work together to define how the internal sequencer
sets bits in the IRQ_STATUS register (and as a consequence, asserting the INT pin).
The PS1 interrupts are described in Table 8. The PS2 interrupts are described in Table 9. The PS2 interrupts are
described in Table 10. The ALS interrupts are described in Table 11, and the Command Interface interrupts are
described in Table 12.
Preliminary Rev. 0.5
21
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