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MAX1202ACAP

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

+3.3V

DOUT

3kΩ

DOUT

3kΩ

CLOAD

CLOAD

GND

GND

a. High-Z to VOH and VOL to VOH

b. High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable Time

+3.3V

DOUT

3kΩ

DOUT

3kΩ

GND

CLOAD

CLOAD

GND

a. VOH to High-Z

b. VOL to High-Z

Figure 2. Load Circuits for Disable Time

CS 18

SCLK 19

DIN 17

SHDN 10

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

CH0 1

CH1 2

CH2 3

CH3 4

CH4 5

CH5 6

CH6 7

CH7 8

GND 13

REFADJ 12

REF 11

OUTPUT 15 DOUT

SHIFT

REGISTER

16

SSTRB

ANALOG

INPUT

MUX

T/H

CLOCK

IN 12-BIT

SAR

MAX1202

MAX1203

ADC OUT

REF

20 VDD

+2.44V

REFERENCE

A

20kΩ

ª 1.68

(MAX1202)

14 VL

9

VSS

+4.096V

Figure 3. Block Diagram

Detailed Description

The MAX1202/MAX1203 analog-to-digital converters

(ADCs) use a successive-approximation conversion tech-

nique and input track/hold (T/H) circuitry to convert an

analog signal to a 12-bit digital output. A flexible serial

interface provides easy interface to 3V microprocessors

(μPs). Figure 3 is the MAX1202/MAX1203 block diagram.

Pseudo-Differential Input

Figure 4 shows the ADC’s analog comparator’s sampling

architecture. In single-ended mode, IN+ is internally

switched to CH0–CH7 and IN- is switched to GND. In

differential mode, IN+ and IN- are selected from pairs of

CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure

the channels using Tables 3 and 4.

In differential mode, IN- and IN+ are internally switched to

either of the analog inputs. This configuration is pseudo-

differential such that only the signal at IN+ is sampled.

The return side (IN-) must remain stable (typically within

±0.5 LSB, within ±0.1 LSB for best results) with respect

to GND during a conversion. To do this, connect a 0.1μF

capacitor from IN- (of the selected analog input) to GND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends on

the falling SCLK edge after the input control word’s last bit

is entered. The T/H switch opens at the end of the acquisi-

tion interval, retaining charge on CHOLD as a sample of

the signal at IN+.

The conversion interval begins with the input multiplexer

switching CHOLD from the positive input (IN+) to the nega-

tive input (IN-). In single-ended mode, IN- is simply GND.

This unbalances node ZERO at the comparator’s input.

The capacitive DAC adjusts during the remainder of the

conversion cycle to restore node ZERO to 0V within the

limits of 12-bit resolution. This action is equivalent to trans-

ferring a charge of 16pF x [(VIN+) - (VIN-)] from CHOLD to

the binary-weighted capacitive DAC, which in turn forms a

digital representation of the analog input signal.

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