MAX1202ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1202ACAP

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

Typical Operating Characteristics (continued)

(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C, unless other-

wise noted.)

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

0

INTEGRAL NONLINEARITY

vs. DIGITAL

750 1500 2250 3000 3750 4500

DIGITAL CODE

20

0

-20

-40

-60

-80

-100

-120

0

FFT PLOT

VSS = -5V

33.25

FREQUENCY (kHz)

66.50

Pin Description

PIN

NAME

1–8

CH0–CH7

9

VSS

10

SHDN

11

REF

12

REFADJ

13

GND

14

VL

15

DOUT

16

SSTRB

17

DIN

18

CS

19

SCLK

20

VDD

FUNCTION

Sampling Analog Inputs

Negative Supply Voltage. Tie VSS to -5V ±5% or to GND.

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)

supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to VDD puts

the reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the

reference-buffer amplifier in external compensation mode.

Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the

reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external

reference mode, disable the internal buffer by pulling REFADJ to VDD.

Input to the Reference-Buffer Amplifier. Tie REFADJ to VDD to disable the reference-buffer amplifier.

Ground; IN- Input for Single-Ended Conversions

Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of

the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.

Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin

the analog-to-digital conversion, and goes high when the conversion is finished. In external clock

mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is

high (external clock mode).

Serial-Data Input. Data is clocked in at SCLK’s rising edge.

Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK

also sets the conversion speed (Duty cycle must be 40% to 60% in external clock mode).

Positive Supply Voltage, +5V ±5%

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