MAX1202ACAP(1998) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1202ACAP
(Rev.:1998)

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

CLOCK

MODE

SHDN

DIN

INTERNAL

SETS EXTERNAL

CLOCK MODE

SXXXXX11

EXTERNAL

SXXXXX0 1

SETS FAST

POWER-DOWN

MODE

SETS EXTERNAL

CLOCK MODE

S XX XXX1 1

DOUT

MODE

DATA VALID

(12 DATA BITS)

POWERED UP

DATA VALID

(12 DATA BITS)

POWERED UP

FAST

POWER-DOWN

Figure 12a. Timing Diagram for Power-Down Modes, External Clock

EXTERNAL

DATA

INVALID

FULL

POWER-

DOWN

POWERED

UP

Table 5. Typical Power-Up Delay Times

REFERENCE

BUFFER

Enabled

Enabled

Enabled

Disabled

Disabled

REFERENCE-BUFFER

COMPENSATION MODE

Internal

Internal

External

REF

CAPACITOR

(µF)

4.7

POWER-DOWN

MODE

Fast

Full

Fast/Full

Fast

Full

POWER-UP

DELAY

(µs)

5

300

See Figure 14c

2

2

MAXIMUM

SAMPLING RATE

(ksps)

26

26

133

133

133

Table 6. Software Shutdown

and Clock Mode

PD1

PD0

DEVICE MODE

0

0

Full power-down mode

0

1

Fast power-down mode

1

0

Internal clock mode

1

1

External clock mode

Table 7. Hard-Wired Shutdown

and Compensation Mode

SHDN

STATE

VDD

Floating

GND

DEVICE

MODE

Enabled

Enabled

Full

Power-Down

REFERENCE-BUFFER

COMPENSATION

Internal compensation

External compensation

N/A

18 ______________________________________________________________________________________

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