74LVC08APW/AUJ 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC08APW/AUJ Datasheet PDF : 15 Pages
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Nexperia
74LVC08A
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
6. Functional description
Description
data input
data input
data output
ground (0 V)
supply voltage
Table 3. Function selection[1]
Input
nA
nB
L
X
X
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Output
nY
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Ptot
Tstg
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
VI < 0 V
VO > VCC or VO < 0 V
output HIGH or LOW-state
VO = 0 V to VCC
Tamb = 40 C to +125 C
0.5
50
[1] 0.5
-
[2] 0.5
-
-
100
[3]
-
65
+6.5 V
-
mA
+6.5 V
50
mA
VCC + 0.5 V
50
mA
100
mA
-
mA
500
mW
+150 C
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC08A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 19 April 2016
© Nexperia B.V. 2017. All rights reserved
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