74HC573 데이터 시트보기 (PDF) - NXP Semiconductors.
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74HC573 Datasheet PDF : 21 Pages
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NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Control
OE
LE
Enable and read register (transparent
L
H
mode)
Latch and read register
L
L
Latch register and disable outputs
H
L
Input
Dn
L
H
l
h
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
Internal
latches
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
DIP20 package
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
0.5
-
-
-
-
-
65
[1] -
[2] -
+7
V
20 mA
20 mA
35 mA
+70 mA
70 mA
+150 C
750 mW
500 mW
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
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