74ALVT16823DGG,118 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74ALVT16823DGG,118

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Nexperia B.V. All rights reserved 

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nCE

nCP

nMR

nOE

Figure 3. Logic diagram

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nD8

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

CP

nD

RQ

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

nQ8

001aad243

74ALVT16823

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 22 January 2018

© Nexperia B.V. 2018. All rights reserved.

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