P101K 데이터 시트보기 (PDF) - Vishay Semiconductors
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P101K Datasheet PDF : 6 Pages
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P100 Series
Vishay High Power Products Passivated Assembled
Circuit Elements, 25 A
ON-STATE CONDUCTION
PARAMETER
SYMBOL
Maximum DC output current
at case temperature
ID
Maximum peak, one-cycle
non-repetitive on-state or
forward current
ITSM,
IFSM
Maximum I2t for fusing
I2t
Maximum I2√t for fusing
Maximum value of
threshold voltage
Maximum level value of on-state
slope resistance
Maximum on-state voltage drop
Maximum forward voltage drop
Maximum non-repetitive rate of
rise of turned-on current
Maximum holding current
Maximum latching current
I2√t
VT(TO)
rt1
VTM
VFM
dI/dt
IH
IL
TEST CONDITIONS
Full bridge
t = 10 ms
t = 8.3 ms
No voltage
reapplied
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
100 % VRRM
reapplied
No voltage
reapplied
Sinusoidal half wave,
initial TJ = TJ maximum
t = 10 ms
t = 8.3 ms
100 % VRRM
reapplied
t = 0.1 to 10 ms, no voltage reapplied
I2t for time tx = I2√t · √tx
TJ = 125 °C
VALUES
25
85
357
375
300
315
637
580
450
410
6365
0.82
TJ = 125 °C, average power = VT(TO) x IT(AV) + rt + (IT(RMS))2
TJ = 25 °C, ITM = π x IT(AV)
TJ = 25 °C, ITM = π x IT(AV)
TJ = 125 °C from 0.67 VDRM
ITM = π x IT(AV), Ig = 500 mA, tr < 0.5 µs, tp > 6 µs
TJ = 25 °C anode supply = 6 V, resistive load, gate open
TJ = 25 °C anode supply = 6 V, resistive load
12
1.35
1.35
200
130
250
UNITS
A
°C
A
A2s
A2√s
V
mΩ
V
V
A/µs
mA
BLOCKING
PARAMETER
Maximum critical rate of rise of
off-state voltage
Maximum peak reverse
and off-state leakage current
at VRRM, VDRM
Maximum peak reverse
leakage current
RMS isolation voltage
SYMBOL
dV/dt
IRRM,
IDRM
IRRM
VISOL
TEST CONDITIONS
TJ = 125 °C, exponential to 0.67 VDRM gate open
TJ = 125 °C, gate open circuit
TJ = 25 °C
50 Hz, circuit to base, all terminals shorted,
TJ = 25 °C, t = 1 s
VALUES
200
UNITS
V/µs
10
mA
100
µA
2500
V
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For technical questions, contact: ind-modules@vishay.com
Document Number: 93754
Revision: 03-Jun-08
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