UPD4715AGT 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD4715AGT

Line driver/receiver

NEC => Renesas Technology 

BLOCK DIAGRAM/PIN CONFIGURATION (Top View)

µPD4715A

+

C1

+5V

Bypass

capasitor

+10V

+

C3

1 VDD

2 C1+

3 VCC

4 C1–

5 GND

DIN1 6

TTL/CMOS

INPUT

DIN2 7

DIN3 8

DIN4 9

DIN5 10

Output control DCON 11

TTL/CMOS

OUTPUT

ROUT1 12

ROUT2 13

ROUT3 14

DC - DC

converter

C4+ 28

GND 27

C4– 26

+

C4

+

C2

VSS 25

–10V

24 STBY Standby

5 kΩ

300 Ω

300 Ω

300 Ω

300 Ω

300 Ω

23 DOUT1

22 DOUT2

21 DOUT3

20 DOUT4

19 DOUT5

18 RIN1

17 RIN2

5 kΩ

16 RIN3

RS-232

OUTPUT

RS-232

INPUT

5 kΩ

15 RCON

Threshold control

* VDD and Vss are output pins of voltages internally boosted. Connecting a load directly to these pins is not

recommended.

** The standby pin is internally pulled down.

*** Use capacitors with a working voltage of 16 V or higher as C1 through C4. Insert a bypass capasitor about 0.1

to 1 µF between VCC pin to GND pin.

2

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