MAX1473ETJ(2003) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1473ETJ
(Rev.:2003)

315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range

Maxim Integrated 

315MHz/433MHz ASK Superheterodyne

Receiver with Extended Dynamic Range

Detailed Description

The MAX1473 CMOS superheterodyne receiver and a

few external components provide the complete receive

chain from the antenna to the digital output data.

Depending on signal power and component selection,

data rates as high as 100kbps can be achieved.

The MAX1473 is designed to receive binary ASK data

modulated in the 300MHz to 450MHz frequency range.

ASK modulation uses a difference in amplitude of the

carrier to represent logic 0 and logic 1 data.

Low-Noise Amplifier

The LNA is an NMOS cascode amplifier with off-chip

inductive degeneration that achieves approximately

16dB of power gain with a 2.0dB noise figure and an

IIP3 of -12dBm. The gain and noise figure are depen-

dent on both the antenna matching network at the LNA

input and the LC tank network between the LNA output

and the mixer inputs.

The off-chip inductive degeneration is achieved by

connecting an inductor from LNASRC to AGND. This

inductor sets the real part of the input impedance at

LNAIN, allowing for a more flexible input impedance

match, such as a typical PC board trace antenna. A

nominal value for this inductor with a 50Ω input imped-

ance is 15nH, but is affected by PC board trace. See

Typical Operating Characteristics for the relationship

between the inductance and the LNA input impedance.

The AGC circuit monitors the RSSI output. When the

RSSI output reaches 2.05V, which corresponds to an

RF input level of approximately -57dBm, the AGC

switches on the LNA gain reduction resistor. The resis-

tor reduces the LNA gain by 35dB, thereby reducing

the RSSI output by about 500mV. The LNA resumes

high-gain mode when the RSSI level drops back below

1.45V (approximately -65dBm at RF input) for 150ms.

The AGC has a hysteresis of ~8dB. With the AGC func-

tion, the MAX1473 can reliably produce an ASK output

for RF input levels up to 0dBm with a modulation depth

of 18dB.

The LC tank filter connected to LNAOUT comprises L3

and C2 (see Typical Application Circuit). Select L3 and

C2 to resonate at the desired RF input frequency. The

resonant frequency is given by:

f=

1

2π LTOTAL × CTOTAL

where:

LTOTAL = L3 + LPARASITICS

CTOTAL = C2 + CPARASITICS

LPARASITICS and CPARASITICS include inductance and

capacitance of the PC board traces, package pins,

mixer input impedance, LNA output impedance, etc.

These parasitics at high frequencies cannot be

ignored, and can have a dramatic effect on the tank fil-

ter center frequency. Lab experimentation should be

done to optimize the center frequency of the tank.

Mixer

A unique feature of the MAX1473 is the integrated

image rejection of the mixer. This device eliminates the

need for a costly front-end SAW filter for most applica-

tions. Advantages of not using a SAW filter are

increased sensitivity, simplified antenna matching, less

board space, and lower cost.

The mixer cell is a pair of double balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz IF from a low-side injected LO (i.e., fLO = fRF -

fIF). The image-rejection circuit then combines these

signals to achieve a minimum 45dB of image rejection

over the full temperature range. Low-side injection is

required due to the on-chip image rejection architec-

ture. The IF output is driven by a source-follower biased

to create a driving impedance of 330Ω; this provides a

good match to the off-chip 330Ω ceramic IF filter. The

voltage conversion gain is approximately 13dB when

the mixer is driving a 330Ω load.

The IRSEL pin is a logic input that selects one of the

three possible image-rejection frequencies. When

VIRSEL = 0V, the image rejection is tuned to 315MHz.

VIRSEL = VDD/2 tunes the image rejection to 375MHz,

and when VIRSEL = VDD, the image rejection is tuned to

433MHz. The IRSEL pin is internally set to VDD/2 (image

rejection at 375MHz) when it is left floating, thereby

eliminating the need for an external VDD/2 voltage.

Phase-Locked Loop

The PLL block contains a phase detector, charge

pump/integrated loop filter, VCO, asynchronous 64x

clock divider, and crystal oscillator driver. Besides the

crystal, this PLL does not require any external compo-

nents. The VCO generates a low-side local oscillator

(LO). The relationship between the RF, IF, and refer-

ence frequencies is given by:

where:

fREF = (fRF - fIF) / (32 ✕ M)

M = 1 (VXTALSEL = VDD) or 2 (VXTALSEL = 0V)

To allow the smallest possible IF bandwidth (for best

sensitivity), the tolerance of the reference must be mini-

mized.

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