CXA3562R 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA3562R

LCD Driver

Sony Semiconductor 

CXA3562R

Pin Description

Pin

No.

Symbol

2 MCLK

3 MCLKX

I/O

Standard

voltage level

VDD

PECL

differential

(amplitude

I 0.4V or more 2

between

3

VDD to 2V)

or TTL input

GND

Equivalent circuit

Description

140k

1k

1k

60k

8k 140k

Dot clock input.

PECL differential input or TTL

input. For TTL input, input to

MCLK and connect MCLKX to

GND through a capacitor.

100µ 60k

4 FRP

I

High: ≥2.0V

Low: ≤0.8V

VDD

4

50k

192

GND

LCD panel AC drive inversion

timing input.

High: inverted

Low: non-inverted

See the Timing Chart.

5 SHST

I

High: ≥2.0V

Low: ≤0.8V

VDD

5

50k

192

GND

Internal sample-and-hold timing

circuit reset pulse input.

This pin is also used as the

offset cancel level insertion

timing input.

A reset is applied to the internal

timing generator at the falling

edge.

6 POSCTR0

7

8

POSCTR1

POSCTR2

I

High: ≥2.0V

Low: ≤0.8V

9 POSCTR3

VDD

68

79

GND

50k

192

Output phase adjustment.

The output phase is adjusted in

MCLK period units when

SL_DAT (Pin 72) is high, and in

1/2 MCLK period units when

SL_DAT is low.

16 SIG.C

I 1 to 5.0V

VDD

VCC

20µ

Signal center voltage (inversion

30k

16

folded voltage) adjustment input.

The SH_OUT output center

voltage can be adjusted in the

range from 7.0 to 8.0V.

GND

17 SIG_OFST I 0 to 5.0V

VDD

30k

17

VCC

10µ

GND

Output signal offset adjustment

from signal center voltage.

The SH_OUT output 100%

white level (at 3FF input) voltage

can be adjusted in the range

from 0 to 1V from the center

voltage.

–3–

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